The current levels in Electrostatic Discharge (ESD) events are generally in excess of 1 amp for durations of between a few nanoseconds to 100 nanoseconds, and can cause severe damage in Integrated Circuits (ICs). The most sensitive areas of an IC are the devices which are directly connected to bondpads. In order to protect the input/output (I/O) buffers from the ESD stress, protection circuits which act as voltage clamps and current shunts are placed in parallel with the I/O circuits. The purpose of the ESD protection circuit is to turn on during the ESD event and clamp the voltage before the I/O buffer is damaged.
The design and optimization of ESD protection circuits is greatly enhanced by the ability to perform circuit level simulations of the protection circuits and the I/O buffers. Most available simulators do not address the high current region of the circuit operation, but still enable an approximate analysis to be made of the behavior under ESD conditions. The growing use of MOS-based protection circuits (rather than the SCR-type structures), and the integration of the protection circuits with the internal circuitry, lead to a need for simulators which are able to more accurately reproduce the behavior of the circuit under ESD conditions.
During an ESD event, the internal gates of the chip could be at different potentials depending on the coupling of the power supply bus to the ESD voltage. The turn on of the ESD protection circuit and its effectiveness becomes dependent on the turn on behavior of the I/O buffers and the state of the internal logic during the stress. Hence, it is an object of the instant invention to provide an ESD circuit simulator that includes the high current behavior of the MOS transistors under gate bias conditions. It also is an object of the instant invention to provide a simulator that simulates circuit operation during an Electrical Overstress (EOS) or overvoltage stress under power-up conditions to be determined.
Existing simulation methods use models which are impossible to practically implement in an MOS ESD simulator. This greatly reduces their effectiveness and their usage. Hence, it is an object of the instant invention to provide a simple and practical parameter extraction methodology which is essential for the application of the simulator.
It is, therefore, an object of the instant invention to provide a method for simulating the effects of an ESD-type stress on a full I/O circuit, and to identify the current paths and internal node voltages during the stress. It is also an object of the instant invention to provide a method for simulating the effects of a parasitic bipolar transistor in parallel with an MOS device so as to optimize I/O circuits with regards to normal operation and overvoltage events.